Analysis and characterization of random skew and jitter in a novel clock network

System clock uncertainty, in the form of random skew and jitter, is beginning to affect performance of large microprocessors significantly. Process and environmental variations and inter-signal coupling on a chip contribute significant delay variations in long clock lines, and these variations are predicted to make the now widely-used clock tree distribution untenable. Distributed clock generation may allow clock networks to continue scaling with advances in semiconductor processing technology. A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable large-signal stable (modelocked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. The circuits were fabricated in CMOS, and two implementations of the system — a 4 oscillator proof-of-concept 400MHz network, and a 16-oscillator, 1.3GHz network network are presented. A flash time-to-digital converter is presented that exploits parallelism to get precise time measurements with resolution much smaller than a single gate delay. Unfortunately, an unrelated failure precluded measurements on the 16-oscillator chip where the measurement system was integrated, but the principle is shown to be valid on an independent test chip. Thesis Supervisor: Anantha Chandrakasan Title: Associate Professor of Electrical Engineering Analysis and Characterization of Random Skew and Jitter in a Novel Clock Network by Vadim Gutnik Submitted to the Department of Electrical Engineering and Computer Science on March 3, 2000, in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering Abstract System clock uncertainty, in the form of random skew and jitter, is beginning to affect performance of large microprocessors significantly. Process and environmental variations and inter-signal coupling on a chip contribute significant delay variations in long clock lines, and these variations are predicted to make the now widely-used clock tree distribution untenable. Distributed clock generation may allow clock networks to continue scaling with advances in semiconductor processing technology. A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable large-signal stable (modelocked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. The circuits were fabricated in CMOS, and two implementations of the system — a 4 oscillator proof-of-concept 400MHz network, and a 16-oscillator, 1.3GHz network network are presented. A flash time-to-digital converter is presented that exploits parallelism to get precise time measurements with resolution much smaller than a single gate delay. Unfortunately, an unrelated failure precluded measurements on the 16-oscillator chip where the measurement system was integrated, but the principle is shown to be valid on an independent test chip.System clock uncertainty, in the form of random skew and jitter, is beginning to affect performance of large microprocessors significantly. Process and environmental variations and inter-signal coupling on a chip contribute significant delay variations in long clock lines, and these variations are predicted to make the now widely-used clock tree distribution untenable. Distributed clock generation may allow clock networks to continue scaling with advances in semiconductor processing technology. A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable large-signal stable (modelocked) states dictate the transfer characteristic of the phase detectors; a matrix formulation of the linearized system allows direct calculation of system poles for any desired oscillator configuration. The circuits were fabricated in CMOS, and two implementations of the system — a 4 oscillator proof-of-concept 400MHz network, and a 16-oscillator, 1.3GHz network network are presented. A flash time-to-digital converter is presented that exploits parallelism to get precise time measurements with resolution much smaller than a single gate delay. Unfortunately, an unrelated failure precluded measurements on the 16-oscillator chip where the measurement system was integrated, but the principle is shown to be valid on an independent test chip. Thesis Supervisor: Anantha Chandrakasan Title: Associate Professor of Electrical Engineering